XC9500系列芯片主要特征介绍及解密

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   最近，龙芯科技芯片解密服务中心针对Xilinx芯片的整体攻关为大家的解密项目带来了佳音，下文介绍关于XC9500系列芯片的主要特性供大家参考：
Features
•High-performance-5 ns pin-to-pin logic delays on all pins
-fCNT to 125 MHz
•Large density range
-36 to 288 macrocells with 800 to 6,400 usable gates
•5V in-system programmable
-Endurance of 10,000 program/erase cycles
-Program/erase over full commercial voltage and temperature range
•Enhanced pin-locking architecture
•Flexible 36V18 Function Block
-90 product terms drive any or all of 18 macrocells within Function Block
-Global and product term clocks, output enables,set and reset signals
-Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
-Programmable power reduction mode in each macrocell
-Slew rate control on individual outputs
-User programmable ground pin capability
-Extended pattern security features for design protection
-High-drive 24 mA outputs
-3.3V or 5V I/O capability
-Advanced CMOS 5V Fast FLASH™ technology
-Supports parallel programming of multiple XC9500 devices
Family Overview
   The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance,general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles.Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.
   As shown in Table 1, logic density of the XC9500 devicesranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 fam-ily is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint.
   The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades.
   Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be configured for 3.3V or 5V operation. All outputs provide 24 mA drive.
 　以上是我们针对Xilinx单片机的主要特征进行简单介绍，供广大客户及其他芯片解密工程师在解密项目合作及芯片技术应用中参考借鉴。如果客户有XC9500芯片解密以及其他单片机解密需求，请与龙芯世纪科技联系咨询更多合作详情
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